1. Field of the Invention
This invention relates to a semiconductor dynamic random access memory having an array of memory cells comprising an information storage capacitor and an access transistor.
2. Decription of the Prior Art
An integrated circuit dynamic random access memory (DRAM) comprises an array of memory cells arranged in rows and columns. For example, an array of 256 rows and 256 columns provides 65,536 memory cells. A given integrated circuit chip or wafer may comprise a multiplicity of arrays, with each array then usually referred to as a "sub-array". The memory cell itself usually comprises an information storage capacitor that communicates with a column conductor through a field effect transistor, referred to as the access transistor. A high voltage level, referred to as a "1", or a low voltage level, referred to as a "0", can be stored in the capacitor. A typical memory array is illustrated in FIG. 1.
To access a given memory cell in the array, a column decoder selects a column conductor for connection to a data input/output (I/O) line. An adjacent "complement" column conductor is also selected in most designs. The column conductors are frequently referred to as "bit lines", and connect to one side of the access transistors in the column. The electrode of a field effect access transistor connected to the column conductor serves alternately as the "drain" or the "source" of the transistor, depending on the voltage between the column conductor and the storage capacitor. A given memory cell is selected when the row conductor for that memory cell is also selected by the row decoder. Activating a row conductor, also referred to as a "word line", allows the access transistor in the selected row to conduct.
Referring to FIG. 1, an exemplary n-channel access transistor M11 conducts when the row conductor R1 is placed at a high voltage level by the row decoder. Then, access to the storage capacitor 10 from column conductor C1 is possible. However, the threshold voltage drop across M11 reduces the voltage that can be written into the storage capacitor. Thus, if the threshold voltage, Vth, of M11 is 1.5 volts, and the accessed row conductor raises the gate voltage on M11 to 5 volts, then a 5 volt write signal on C1 produces only 5-1.5=3.5 volts on the capacitor 10. This reduction in the stored magnitude of the data written into the cell has a deleterious effect on the reliability of subsequently reading the data from the cell.
To counter the effect of the threshold voltage drop, prior art memories employ a "boosted word line", wherein the voltage on a selected row is increased above the power supply level. Referring to FIG. 2, the row selection process is initiated when the RE signal goes low. In one prior art technique, the word line voltage is boosted above the positive power supply voltage during the entire memory cycle (curve A). A boosted voltage of 7 to 8 volts is typical for memories having a nominal 5 volt positive power supply. However, the boosted voltage places stress on the access transistors connected thereto. This stress increases as transistor geometries, and especially gate insulator thicknesses, decrease. Furthermore, boosting for the entire memory cycle places corresponding demands on the boost generator circuit, which must supply any leakage currents. Also, for a given boost generator design, the variability of the leakage curents from chip to chip reduces the yield of usable chips. Therefore, an alternate prior art technique (curve B) supplies the boosted voltage only during the refresh portion of the memory cycle, which is initiated when RE goes high. At other times during the cycle, the selected word line is allowed to remain at the positive power supply level, Vcc.
This latter technique reduces electrical stress on the access transistors and reduces yield limiting leakage problems, while ensuring that a full high voltage level is refreshed in those cells storing a "1". This full refresh level also extends the time period between required refreshes, a desirable result. (This time period is essentially determined by the length of time that the storage capacitor can maintain a high enough voltage to ensure adequate margins for subsequent readout.) Note also that the refresh period occurs near the end of a memory cycle, before the "recovery" period when the columns are precharged in preparation for the next cycle. Hence, the refresh operation must be accomplished in as short a time as possible, to prevent the overall cycle time from becoming excessively large. The boost during refresh helps to speed the necessary charge transfer during this critical time.